Making Successful Power Distribution Designs

Course summary

  • Mon 26 Jun 2017 to Tue 27 Jun 2017
  • Oxford
  • £995.00
  • Course code O16C704H6Y
  • electronics@conted.ox.ac.uk
  • Applications being accepted
  • Only 1 place left

Making Successful Power Distribution Designs



Overview

Why you should take this course:

  1. This is the best power distribution design course on the market.
  2. It is a course for industry professionals taught by an experienced industry practitioner who does these designs on a daily basis.
  3. The course tutor has many years of teaching experience as a university professor as well as hands-on industry experience.

All delegates attending this course will receive a reference copy of "Power Distribution Network Design Methodologies" by the Course Tutor, Dr Istvan Novak (Originally published by International Engineering Consortium - 15 Jul 2008).


This course is part of Oxford University's High-Speed Digital, Analogue and EMC Engineering Month.

Read Istvan Novak's latest technical newsletter here: The Evergreen Question about PDN: Charge Delivery Time or Impedance.

Programme details

Decoupling and Bypassing Design / Simulation and Measurements of Power Distribution Networks

Day 1:

  • How power integrity, signal integrity and electromagnetic compatibility interact (power distribution noise is very wide band).
  • Calculating worst-case time-domain power-distribution noise.
  • Reverse Pulse Technique, a very powerful, yet simple methodology to find worst-case time-domain PDN noise response.
  • Models of vias and pads, models of various capacitors and power planes - for power distribution applications, losses are our friends. You will learn why and how.
  • DC drop on power planes; optimization of plane voltage drop - we will demonstrate that 1+1 is not always 2.
  • DC-DC converters in the power distribution network, response time vs. output impedance - you will see live oscilloscope demonstrations of good and bad converter behaviour.
  • Minimizing noise by creating flat impedance response, conditions for smooth impedance profiles - flat impedance response is the single most effective way to reduce noise.
  • Bypass capacitor selection: synthesis of 'Multi-pole', 'Big-V', 'Flat' impedance profiles, area capacitors - you will see the strengths and weaknesses of each and we will discuss how to select the solution suitable for your design on a DDR memory PDN example.
  • Stackup/layout considerations, proper location and placement of capacitors, plane splits and plane stitching - plane splits slow down signal edges, radiate, but most importantly, increase crosstalk among signals crossing it.
  • High-frequency response, plane modal resonances and their suppression. Plane resonances and plane-capacitor antiresonance increase noise - we will learn three techniques how to suppress these resonances.
  • Designing PDN filters: low-Q transfer functions, lossy ferrites - you will receive a simple design tool, which we will use in the class to show how to design a good PLL filter.

 

Day 2:

  • Time and frequency-domain description of PDN noise - time domain is better suited for low duty cycle rare, but large noise events. Frequency domain is better to identify any periodic noise component.
  • What you need to know about network matrices: impedance, admittance, scattering, and transfer matrices - we will explain why impedance matrix is the good metric for PDN, yet most measurements require S-parameters.
  • Linear network characteristics, time and frequency-domain simulations, moving between the domains - we will show many of the common pitfalls when FFT/IFFT is used to generate PDN response.
  • Simulating and measuring DC drop - we will illustrate by simulations and live measurements the three-dimensional nature of current distribution at DC.
  • Measurement solutions for PDN; selection of probes and instruments, two-port VNA measurements - the two-port measurement is the only usable approach for measuring low-impedance PDN.
  • How to select instruments to do the job without overspending. 
  • The little dirty secret of application notes: why many suggest (wrongly!) to measure noise across capacitors.
  • Modelling, simulation and measurement of bypass capacitors, ferrites and inductors - some ceramic capacitors and ferrites exhibit strong dependence on DC and AC bias.
  • How to simulate and measure DC and AC bias effects.
  • Modelling, simulation and measurement of DC-DC converters - there are a few important DC-DC converter parameters, which practically can not be simulated. You will learn which those are and how to handle them.
  • Modelling, simulation and measurement of vias - you will learn why most blind vias can carry more current than plated through holes.
  • Modelling, simulation and measurement of power planes and systems.
  • Measuring power planes at high frequencies require very good connection techniques - we will show case studies when you need 1D, 2D or 3D simulators for power planes.

 

First day registration from 8.30am when course materials will be distributed.
Refreshments from 8.30am on the first day plus two 30 minute breaks during the day and a one-hour lunch break.
The course will begin at 9.00am and end at approximately 5.00pm on each day.

Certification

Participants who satisfy the course requirements will receive a Certificate of Attendance. The sample is an illustration only.

Accommodation

Accommodation is available at the Rewley House Residential Centre, within the Department for Continuing Education, in central Oxford. The comfortable, en-suite, study-bedrooms have been rated as 4-Star Campus accommodation under the Quality In Tourism scheme, and come with tea- and coffee-making facilities, free Wi-Fi access and Freeview TV. Guests can take advantage of the excellent dining facilities and common room bar, where they may relax and network with others on the programme.

Accommodation is not included in the course fees.

Fees

Standard course fee: £995.00

Payment

Pay immediately online by credit or debit card

Click the “book now” button on this webpage to pay online with a credit or debit card

Pay later with your preferred payment method

Send a completed application form to the course administrator by e-mail or post, and choose:

  • Request an invoice
  • BACS payment
  • Cheque payment
  • Credit or debit card payment. Please do not send card details via email

 

Fees include course materials, tuition, refreshments and lunches. The price does not include accommodation.

All courses are VAT exempt.

Tutors

Dr Istvan Novak

Speaker

Senior Principal Engineer
Oracle

Istvan is the Senior Principal Engineer at Oracle working on new advanced power distribution design and validation methodologies. For eleven years prior to this Dr. Novak was responsible for the power distribution and high-speed signal integrity designs of SUN's succesful workgroup server families. He introduced the industry's first 25um power-ground laminates for large rigid computer boards, and worked with component vendors to create a series of low-inductance and controlled-ESR bypass capacitors.

Dr. Novak also served as SUN's representative on the Copper Cable and Connector Workgroup of InfiniBand, and is engaged in the methodologies, designs and characterization of power-distribution networks and CPU packages. He has thirty years of experience with high-speed digital, RF, and analog circuit and system design and has twenty five patents.

He is Fellow of IEEE for his contributions to the signal-integrity and RF measurement as well as simulation methodologies, lead author of the book "Frequency-Domain Characterization of Power Distribution Networks" (Artech House, 2007) and Executive Editor of the book "Power Distribution Design Methodologies" (IEC, 2008).

For additional insight into Dr Novak, please read the EDN Network's Profile in Design.

Application

If you would like to discuss your application or any part of the application process before applying, please contact:
Course Administrator
Tel: +44 (0)1865 286958
Email: electronics@conted.ox.ac.uk

Level and demands

Day 1

 

  • Working Board Design engineers, layout engineers and system designers who are interested in better understanding potential power-distribution problems, and how to overcome these problems with proper component selection and layout techniques.
  • Working signal-integrity and EMI/EMC engineers who are interested in achieving a better understanding of the potential problems caused by improper power distribution designs, and how to correct them.
  • Managers and engineers who are interested in understanding trade-offs of power-distribution design decisions.

     

Day 2

  • Working Board Design engineers, system designers and signal-integrity and EMI/EMC engineers who are interested in better simulation and measurement techniques.
  • Managers and engineers who are interested in understanding the simulation and measurement needs of power distribution networks.

     

    If you're uncertain whether this course is suitable for your requirements, please email us with any questions you may have.