Resetting Your Signal Integrity Knowledge

Course details


Wed 24 Jun 2020 - Fri 26 Jun 2020

Resetting Your Signal Integrity Knowledge


About the course

Signal integrity has been around for a few decades and by now it matured to a discipline that many may think does not hold any new surprises.  On the contrary, people actively working in the field find new challenges and revelations very frequently.  This brand new course summarizes some of the most important and often-times counter-intuitive aspects of signal integrity that are a MUST for all engineers whether they work at relatively low speed or on cutting-edge signalling.  Each major topic starts with a brief overview of the basics, followed by a unique blend of live measurements and simulations to illustrate challenges, constraints, limitations and solutions to scenarios not covered in similar courses.

Who is it for?

  • Board design engineers, system designers and signal-integrity specialists who are interested in a broader and better understanding of potential signal integrity issues.
  • Managers and engineers who are interested in understanding the simulation and measurement challenges and solutions in signal integrity.

Programme details

Day 1:


  • why SI engineers need to know the basics of PI and EMC
  • illustrations of how these disciplines can interact in unexpected ways in our designs

Impedance, reflections, matching:

  • after a brief summary of reflections, transmissions and S parameter, we discuss how much reflection is too much and look at the untold perils of periodicity

PCB and cable constructions

  • what we don’t know about the materials and processes can hurt our design
  • stackup nuances that matter for signal integrity
  • why knowing the laminate parameters alone is not enough to determine losses


  • how different types of vias influence signal integrity
  • when do you need to worry about bends
  • the full picture
  • how to optimize via transitions
  • when does it matter

Day 2:


  • the hidden far-end crosstalk in stripline
  • how to reduce crosstalk in microstrip
  • how a very important PDN measurement principle must be applied to crosstalk measurements and what happens if we ignore it

Differential signaling

  • sorting out the age-old question; 'Should I use loosely or tightly coupled traces?'
  • potential problems and solutions for delay-meander traces
  • when skew will hurt your design

System SI

  • clock and signal routing
  • system performance metrics
  • how we got from setup-hold to signal-to-noise ratio and lately to Channel Operating Margin (COM)

SI measurements and simulations:

  • why you need to know where the calibration's reference plane is
  • what the calibration options are
  • how to choose among them
  • Important rules to keep in mind for simulations
  • The challenges of and helpful suggestions for correlations


Participants who attend the full course will receive a University of Oxford certificate of attendance. This will be presented to you prior to the end of the course wherever possible.

The certificate will show your name, the course title and the dates of the course you attended.


Although not included in the course fee, accommodation may be available at our on-site Rewley House Residential Centre. All bedrooms are en suite and decorated to a high standard, and come with tea- and coffee-making facilities, free Wi-Fi access and Freeview TV. Guests can take advantage of the excellent dining facilities and common room bar, where they may relax and network with others on the programme.

To check prices, availability and to book rooms please visit the Rewley House Residential Centre website. 


Course fee: £995.00


Fees include course materials, tuition, refreshments and lunches. The price does not include accommodation.

All courses are VAT exempt.

Register immediately online 

Click the “book now” button on this webpage. Payment by credit or debit card is required.

Request an invoice

Send a completed application form to the course administrator by email or post. Please do not send card details via email.


Dr Istvan Novak

Course Tutor

Senior Principal Engineer

Istvan is the Senior Principal Engineer at Oracle working on new advanced power distribution design and validation methodologies. For eleven years prior to this Dr. Novak was responsible for the power distribution and high-speed signal integrity designs of SUN's successful workgroup server families. He introduced the industry's first 25um power-ground laminates for large rigid computer boards, and worked with component vendors to create a series of low-inductance and controlled-ESR bypass capacitors.

Dr. Novak also served as SUN's representative on the Copper Cable and Connector Workgroup of InfiniBand, and is engaged in the methodologies, designs and characterization of power-distribution networks and CPU packages. He has thirty years of experience with high-speed digital, RF, and analog circuit and system design and has twenty five patents.

He is Fellow of IEEE for his contributions to the signal-integrity and RF measurement as well as simulation methodologies, lead author of the book "Frequency-Domain Characterization of Power Distribution Networks" (Artech House, 2007) and Executive Editor of the book "Power Distribution Design Methodologies" (IEC, 2008).

For additional insight into Dr Novak, please read the EDN Network's Profile in Design.


If you would like to discuss your application or any part of the application process before applying, please click Contact Us at the top of this page.

Selection criteria

Prerequisite: basic understanding of electronic circuits and waves.