Mastering High-Speed Serial I/O Technology


This 3-day intensive course is for research, design, manufacturing, system, and test engineers; digital and RF engineers; scientists and university students in electrical engineering and physics.

Whether you’re switching fields or want to get caught up to the state of the art, you’ll get what you need.

Ransom Stephens’ high speed serial IO training course helps engineers master electrical signal analysis and hardware debug at data rates from 2.5 to 400 Gb/s.

  • See how three key innovations—differential signaling, clock recovery, and equalization— enabled today’s high data rates; why they’re needed, how they work, and possible alternatives.
  • Master the physical causes of signal distortion—loss, reflections, ISI (inter-symbol interference), crosstalk, and all types of jitter and noise—how to identify them, how to correct them, and, when necessary, how to live with them.
  • Understand  how signals behave in both the time and frequency domains and how to measure and interpret S-parameters, waveforms, eye diagrams, BER (bit error ratio) contours, and bathtub plots using oscilloscopes, VNAs (vector network analyzers), TDR (time-domain reflectometry), BER testers, and spectrum and phase noise analyzers.
  • Explore the bandwidth-complexity trade-off between NRZ and PAM4 signaling schemes for lane rates of 50+ Gb/s and the new measurement techniques for evaluating PAM4 signals along with the pros and cons of forward error correction (RS-FEC). Using examples from cutting edge technologies – PCIe, OIF-CEI, SATA, Fiber Channel, 50-400 Gigabit Ethernet 

This intensive course delivers a complete technical understanding of potential trouble spots in high speed components and systems, compliance, hardware debug, and functional testing.

"It’s an intense three days, but we’ll have a good time!" Ransom Stephens, Course Tutor

“Ransom is that teacher, the one who makes you wish you never left school.”  Andy Martwick, Intel

See Ransom's webinar, "Understanding SNDR and all that goes into it," one of Signal Integrity Journal's top 5 webinars of 2019.

See Ransom's article, "PAM4 for Better and Worse" (published in the Signal Integrity Journal on 26 February 2019).

Programme details

1.Introduction to multi-gigabit technology

  • Serdes design considerations—drivers and receivers
  • Embedded and distributed clocks
  • Jitter and noise
  • Differential signaling, strong and weak coupling
  • Introduction to equalization at the transmitter and receiver

2. Waveforms, digits, and degradation

  • Signal and power integrity: reflections, impedance matching, and return paths
  • Dispersion, skin effect, and inter-symbol interference
  • Impulse and pulse response, transfer functions
  • Thinking in the time and frequency domains: S-parameters and impulse response.

3. Errors, jitter, and noise

  • The Bit Error Ratio (BER)
  • Distinguishing phase noise and jitter
  • Analyzing jitter: making tools out of RJ, DJ, and the jitter alphabet soup
  • Jitter separation on BERTs and oscilloscopes
  • Total Jitter at a Bit Error Ratio, Eye height and Eye Width, vertical eye closure (VEC)
  • The dual-Dirac Model, bathtub plots and Q-Scale
  • Eye closure and BER-contours, margin testing

4. Clocks and Clock Recovery

  • Effect of CR bandwidth on measurements and systems
  • Jitter in the frequency domain and the jitter transfer function
  • Data coding and scrambling
  • CR technologies: PLL, PI, DLL
  • Spread spectrum clocking

5. Crosstalk

  • S-parameter description of crosstalk
  • How to find problems caused by crosstalk in eye diagrams, waveforms, and S-parameters
  • Loss-crosstalk-ISI trade-offs: ICR, IXT, ICN, etc
  • Modeling and emulating crosstalk

6. Equalization, SNDR, COM, and ERL

  • Pre/de-emphasis and transmitter feed forward equalization (FFE)
  • CTLE, DFE, and adaptive equalization
  • How equalization can make crosstalk worse
  • Closed eye analysis, distinguishing jitter and noise from channel response
  • Understanding and calculating channel operating margin (COM), effective return loss (ERL), and signal-to-noise and distortion ratio (SNDR)

7. High speed standards compliance and diagnostic testing

  • Overview of HSS standards: 2.5-10 Gb/s, 25, 56, 112 and 224 Gb/s technology, 100 GbE, 400 GbE, PCIe, USB, SAS/sATA, OIF-CEI, etc.
  • Tips on how to read standard specifications
  • Developing a hardware debug strategy
  • How to make test patterns powerful diagnostic tools
  • Transmitter testing
    • Testing transmitter FFE
    • Eye measurements, masks, and histograms
    • Using CRs in test, effects of loop bandwidth on measurement
    • Problems with delay
  • Summary of channel tests
    • S-parameter masks and requirements
    • COM and ERL
    • Crosstalk analysis
  • Receiver tolerance testing
    • How to configure a stressed eye
    • The roles of each stress
    • Jitter tolerance testing and interference tolerance testing
  • PAM4 testing
    • Analyzing PAM4 eyes
    • Level separation mismatch ratio, timing and level deviation, VEC
    • What to expect from emerging standards

Attending Your Course 

Further details will be emailed to you two weeks ahead of your course, which will include registration information. 

Please get in touch if you have not received this information within five working days of the course start date.  

In the meantime, you may wish to plan your travel: Travel information 

"Ransom’s presentations are clear, to the point, and entertaining.” Megan Chura, Keysight Technologies


To complete the course, you will be required to attend and participate in all of the sessions on the course in order to be considered for a certificate. Participants who complete the course will receive a link to download a University of Oxford digital certificate. Information on how to access this digital certificate will be emailed to you after the end of the course.

The certificate will show your name, the course title and the dates of the course you attended. You will also be able to download your certificate or share it on social media if you choose to do so.


Description Costs
Course fee £1525.00


Fees include course materials, tuition, refreshments and lunches. The price does not include accommodation.

All courses are VAT exempt.

Register immediately online 

Click the “book now” button on this webpage. Payment by credit or debit card is required.

Request an invoice

If you require an invoice for your company or personal records, please complete an online application form. The Course Administrator will then email you an invoice. Payment is accepted online, by credit/debit card, or by bank transfer. Please do not send card or bank details via email.


Ransom Stephens

Signal Integrity Specialist

Ransom Stephens, Ph.D. helps engineers advance to the highest data rates by teaching the concepts engineers need to design better systems, better SerDes (Serializer/Deserializer), and better ways to find problems and come up with solutions.

Ransom started in basic research at labs in the US and Europe specializing in digging weak signals out of strong backgrounds. He brought those skills to high speed electronics in 1999 and invented new techniques for signal and noise analysis.

Since 2005, when he started Ransom’s Notes, his seminars have helped thousands of engineers and scientists understand key nuances of their work.

The author of over four hundred articles in the electronics industry, science journals, and magazines on subjects ranging from the analysis of electrodynamics in high rate digital systems to fiber optics to quantum physics, Ransom was named the 2017 Jim Williams ACE Contributor of the Year for content that advances engineering and design.

He has given thousands of speeches across the US, Europe, and Asia and has developed a reputation for making complex topics accessible and funny.


If you would like to discuss your application or any part of the application process before applying, please click Contact Us at the top of this page.

Level and demands

If you're uncertain whether this course is suitable for your requirements, please email us with any questions you may have.


Although not included in the course fee, accommodation may be available at our on-site Rewley House Residential Centre. All bedrooms are en suite and decorated to a high standard, and come with tea- and coffee-making facilities, free Wi-Fi access and Freeview TV. Guests can take advantage of the excellent dining facilities and common room bar, where they may relax and network with others on the programme.

To check prices, availability and to book rooms please visit the Rewley House Residential Centre website.